FIREFOX only

Introduction

The figure 1 shows the oscilloscope synoptic.

The analogical parts includes:

- Two analogs inputs with AC / DC / GND coupling. These inputs have impedances adapted to the commercial probes available,

- One VGA amplifier stage,

- the inputs of the ADC (10bits).

The digital parts includes:

- the outputs of the ADC,

- one input for external triggering,

- one output for the probes calibration,

- one 100MHz low jitter clock with integrated divisor to allow variable sampling,

- one FPGA that contains memory, digital triggering and logic to send/communicate with the PC,

- a DC/DC isolated converter (5VUSB in, -+5V out) with another integrated switched mode supply + charge pump to have 3V3, -3V3 and 2V5,

- a connector that allow to transform DSO to an handheld version by adding a microcontroler, a keyboard, a display and a battery,

- a USB connector + USB interface (FTDI chip) with opto-isolators for the insulation of the fast signals,

The system must be completed with:

PC Version

A dedicaced PC software.

HandHeld Version

One standard µC that have sufficient inputs/outputs. A graphic LCD panel + keyboard + battery. One have to foreseen the FPGA conf. chip (this chip has an upgradable conf. File).

Figure 1: Oscilloscope synoptic

Inputs stage

We are using photomos as switch. Fig. 1 shows the schematic of the two inputs. The signal from the BNC1 goes to a first stage (C5, R5, U2) that cut or no (depending of the U4 position) the DC component. Then the signal goes through the resistor-capacitor bridge that divide it by 40. The signal is not measured directly after C5 (then without attenuation) in order to be protected against overvoltages. The trimcap has to be adjusted in order to match the impedance of the commercial probes. The photomos U1 is used to ground signal. It's parasitic capacitance is constant due to the weak voltage amplitude. U8 is a FET opamp that act as a buffer. The output signals (IN1 & IN2) must have an amplitude in the range of +-1V (then 2Vpp) to match the input requirement of the next stage. The second input (BNC2) is identical to the first one. U7 with U15a and U15b supply the reference voltages for the gain and offset canceling on the VGA (see next sheet).

Figure 1

As we will see further, IN1 (IN2) has to be in the range of +-1V in order for the conversion to be done at full scale. We'll have 10 ranges for the sensitivity:

ADC stage, part I

The IN1 and IN2 signals are symmetrised with U9 and U10 before going to the Voltage Gain controlled Amplifier (VGA). The tunning range is about 100dB thanks to two voltages inputs. The first one (GAIN_DB_X) tune the gain on a logarithmic scale while the second one (GAIN_MAG_X) tune the gain linearly. The ADC COM output give the necessary offset for the differential amplifiers and the VGA. The differential amplifier voltage outputs are the voltage at the positive input raised by an offset of about 1.65V (VCOM). ITX2 and ITX3 connect the digital (next sheets) and analog (this sheet and the previous one) part of the DSO. Then it's foreseen to have two PCB.

Figure 1

ADC stage II

U1 is a 10 bits pipeline type ADC with a max sample frequency of 105MS/s on both channel simultaneously. To avoid track'n hold errors, the ADC will only work at high frequencies. To obtain acquisition at lower frequencies, one will vary the recording samples frequency into the FPGA RAM.

Figure 1

Logic unit

The logic unit has two main elements. U1 is the first one, it's a 100MHz clock. U3 is a FPGA, the EP1K30 (ACEX1K family from Altera). U3 is configured via the green inputs-outputs (JTAG) that come from the first channel (channel A) of the USB chip (see next page). In user mode, the communication with the FPGA will be done via the 4 other green inputs-outputs that comes from the channel B of the USB chip. Then for the PC version, no uC is necessary. For the HandHeld version, all the green inputs-outputs (+ 5 other signals UC_USERx) are also connected to a dedicaced connector (see further). The red inputs-outputs are those for the digital inputs-outputs: a 16 bits digital analyser and a 16 bits digital pattern generator. The internal supply voltage of U15 is 2V5 while the inputs-outputs supply voltage is 3V3 to be compatible with the 5V logic.

Figure 1

USB communication

Fig.1 shows the schematic. Now, we use a new chip from FTDI: the FT2232C that has the particularity to offer two independent channels, each with several bits. The first one (channel A) will serve as a JTAG programmer to configure the FPGA. The second one (channel B) will serve as a fast serial communication pipe (about 5MS/s) to drive and retrieve datas from the FPGA. To see all the other possibilities that the FT2232C offer, check the datasheet on the FTDI website. In order to isolate the DSO from the PC, U6 and U7 are used as galvanic isolators (with very low consumption) and take place between the USB chip and the remaining parts of the DSO.

Figure 1

Supply and connectors

Fig. 1 shows the schematic. USB_5V is the voltage from the USB schematic (see the previous page). This voltage is converted by U11, an isolated DC/DC converter from TRAGO (5V/500mA). The supply for the analogic parts are filtered (5V, -5V and 3V3). The 2V5 and 3V3 voltage are given by U13, a double step down switching device (in 10 leads-MSOP package!), from the +5VDG. U12is a charge pump that gives the -5V. ITX4, ITX5 and ITX6 are male polarised IDC connectors with respectively 50, 34 and 34 contacts. ITX4 is the interface for the handheld option of the DSO: display, board, battery and µC will be added in this case. ITX5 is the connector for the 16 inputs of the digital analyser and ITX6 is for the 16 outputs of the digital pattern generator. U14, U15, U16 and U17 are the latch, they are protected against overvoltage with 1kohm resistors.

Figure 1